The present invention relates to a dynamic circuit formed on a semiconductor integrated circuit, and relates more particularly to a leakage correcting circuit of a dynamic logical circuit having a pre-charging function which is used, for example, in a dynamic circuit of a digital signal processor.
FIG. 1 shows a prior-art example of a dynamic logical circuit having a pre-charging function.
In FIG. 1, a source and a drain of a PMOS transistor 2 for a pre-charging are connected between a Vcc node to which a power source potential Vcc is supplied and a signal wiring 5 such as an aluminum wiring, for example, and a first inverter circuit 20 is inserted between a pre-charge control signal input node 1 and the PMOS transistor 2.
Each drain of a plurality (a few to several dozens) of NMOS transistors 9, 10, - - - , 11 is connected (wired NOR connection) in common to the signal wiring 5. Each source of these plurality of NMOS transistors is connected to a ground potential (Vss) node and a selective input signal is applied from input signal nodes 6, 7, - - - , 8 corresponding to each gate.
A second inverter circuit 12 for an output driving is inserted between the signal wiring 5 and a signal output node 13.
On the other hand, a leakage correcting circuit 21 has a source and a drain of PMOS transistor 3 for supplying a leakage correction current connected between the Vcc node and the signal wiring 5 and has a third inverter circuit 4 inserted between the signal wiring 5 and the gate of the PMOS transistor 3.
The leakage correcting circuit 21 is provided to correct a reduction of a potential of the signal wiring 5 due to a leakage current which flows slightly between the drains and the sources of the NMOS transistors even if no voltage is being applied to the gates of the NMOS transistors 9, 10, - - - , 11 of which drains are connected to the signal wiring 5.
In this case, the leakage correction current supply quantity of the leakage correcting circuit 21 is set to correspond to the estimate quantity of the leakage current of the NNOS transistors.
Next, an ideal operation of the dynamic logical circuit will be explained below with reference to a timing waveform diagram shown in FIG. 2.
At first, during a period while the pre-charge control signal input is at an "H" level, the PMOS transistor 2 for pre-charging is set to an ON state by an output of "L" level of the first inverter circuit 20.
Then, the signal wiring 5 is pre-charged to the Vcc potential ("H" level) and the output of the second inverter circuit 12 or the potential of the signal output node 13 is set to an "L" level.
Next, the pre-charge control signal input 1 becomes the "L" level, and when one or a plurality of NMOS transistors are selected and turned on during this period by a selective input signal (only the waveform of the node 6 is shown representatively) of the input signal nodes 6, 7, - - - , 8, the potential of the signal wiring 5 is discharged. When the potential of the signal wiring 5 drops to a level not higher than the threshold voltage of the second inverter circuit 12 for output driving, the potential of the signal output node 13 is inverted to the "H" level.
The PMOS transistor 3 of the leakage correcting circuit 21 remains in the turn-ON state by the "L" level output of the third inverter circuit 4 until when the potential of the signal wiring 5 has dropped to a level not higher than the threshold voltage of the third inverter circuit 4 for supplying a leakage correction current, and the leakage correcting circuit 21 is continuing the supply of the leakage correction current to the signal wiring 5 so as to correct the reduction of the potential of the signal wiring 5 due to the leakage current of the NMOS transistors.
When the potential of the signal wiring 5 drops to a level not higher than the threshold voltage of the third inverter by the above-described logical operation, the PMOS transistor 3 for supplying a leakage correction current is set to the turn-OFF state by the "H" level output of the third inverter circuit 4.
However, there is a case where a malfunction occurs because the actual operation waveform of the dynamic logical circuit becomes as shown in FIG. 3, for example. In other words, since the leakage current of each NMOS transistor increases in proportion to a temperature rise, the leakage current of the NMOS transistors increases to exceed the leakage correction current supply quantity of the leakage correcting circuit 21 when the operation temperature is high. When the potential of the signal wiring 5 has dropped to a level not higher than the estimated value and further dropped to a level not higher than the threshold voltage of the second inverter circuit 12 for output driving as shown in FIG. 3, there occurs such a malfunction that the potential of the signal output node 13 is inverted to the "H" level.
In this case, when the potential of the signal wiring 5 has dropped to a level not higher than the threshold voltage the third inverter circuit 4 for supplying a leakage correction current, the PMOS transistor 3 for supplying a leakage correction current is set to the turn-OFF state by the "H" level output of the third inverter circuit 4, so that the leakage correction current is not supplied.
In order to avoid the above-described malfunction, various countermeasures can be considered such as the driving capacity of the third inverter circuit 4 for supplying a leakage correction current in the leakage correcting circuit 21 is increased or the threshold voltage of the third inverter circuit 4 is lowered.
According to the above countermeasures, however, when only a limited number (for example, only one) of the NMOS transistors is selectively turned on by the selective input signal, the speed for discharging the load of the signal wiring 5 is lowered, with a result that the speed of the logical operation until a normal potential is outputted to the signal output node 13 is lowered.
The Jpn. Pat. Appln. KOKAI Publication No. 5-62490 discloses a technique for deciding whether the potential of a bit line has dropped to a certain level by a leakage of an electrical load and, when the drop has been decided, for preventing a drop of the potential of the bit line due to the leakage by adding a capacity to the bit line, with a view to preventing an error due to the leakage of the electrical load at the time of reading a memory data in a read only semiconductor memory.
The above-described technique, however, does not prevent a malfunction attributable to the fact that the leakage current estimated quantity and the leakage correction current supply quantity are set an imbalanced state depending on the temperature.